Talk to most technical people about the end of “Moore’s Law” and they will pretty much dismiss you. The typical answer being: “people have been saying that for a long time and it has not happened yet”. True but that doesn’t mean it won’t happen.
Is the fact that the sun shines today and yesterday and the day before a promise that it will go on forever? No, of course it is not. Physics gets in the way of that, and so too with Silicon devices.
At the recent OHS summit Andrew Huang (AKA Bunnie) made some remarks about heirloom computers, and they have gained traction/notice elsewhere. While I don’t feel that consumer devices are made to be durable enough at this time to be heirlooms there may be a day when that becomes the case. But more likely than that we will see the amortization of the cost of a FAB driving down the cost of continued production of the same technology. It may be we are about to enter an era of disposable computers.
The truth is we can expect the end of CMOS to be here soon. Perhaps in as little as 5 years.
When people look at Moore’s law from 1971 to at least 2000 they are mostly looking at lithography. The major constraint to producing smaller transistors was reliably drawing small enough lines in plastic (resist).
Now the main drivers are issues related to semiconductor materials. We can draw a few nm line in plastic with an electron beam lithography tool, the approaching problem is atomic.
In early CMOS Aluminum was used as the gate material: Complementary Metal Oxide Semiconductor. The metal disappeared for awhile and we had poly-silicon gate materials. Along the way Copper integration was achieved to help improve conductivity over Aluminum metal layers (integrating Copper into CMOS was non-trivial). This carried forward up to around 65 nm. At 45 nm when we returned to Metal gates with high-k gate stacks.
Though there were other processing changes that were used along the way these are the biggest ones, and it is notable that there were not many larger changes made. It has mostly been a story of one idea and a lot of lithography for 40 years!
The move to high-k gates was needed to allow the gate stack to be thicker. The reason this was needed was gate leakage. At the 65 nm node the gate thickness was about 2 nm or about 12 atoms (S-O has a bond length 154–171 pm). Think about that: 100s of millions of devices all work all with a dozen atoms blocking electrical conduction. The difficulties of a few mislaid atoms were the problem! (Tunneling leakage is exponential with distance).
People talk about the nanoscale but transistors now cost nanocents! (about 100 nanocents each on a current CPU).
What makes Silicon special is not Silicon, but Silicon dioxide. Silicon dioxide is resistant to many chemicals allowing for great chemical selectivity when processing Silicon wafers. Silicon dioxide is stable. And the Silicon/Silicon dioxide interface is a fairly defect free one. The surface recombination at this interface is quite low. (Yes there are dangling bonds and surface roughness that lower carrier mobilities but compared to other interfaces it is a very nice one.) These are some of the amazing properties on the resume of the O and the S in CMOS.
The C is enabled by the relative ease of introducing substitutional impurities into the lattice of the crystal after growth. This feature isn’t really present in compound semiconductors like GaN, where the bond energy is just too high. This combined with self-aligned implantation has played a large roll in CMOS’ long life.
In order to make a FET type transistor, you must form 2 p-n junctions. As the gate length goes down the relative doping of the two sides of this junction must go up. To get reliable device performance these dopings must be consistent. As CMOS continues to scale down this is a major problem.
The distribution of dopants is governed by Poisson statistics. As the number of atoms needed in the channel and source/drain contacts drops the fractional error becomes larger (1/sqrt(N)). Increasing the doping to have a definitive type can reduce this issue however it is not an option above a certain level because of degenerate doping effects.
Part of the solution to this problem is Intel’s fully depleted 22 nm FIN-FETs. These are the first mass produced non-planar transistors, another first for “CMOS”.
I am not even sure if “CMOS” is a good label for what we have now. One thing is for certain, it is only going to get harder to make these transistors. If something else doesn’t stop us first we are going to run into quantum mechanics, specifically tunneling if not localization effects in the not too distant future.
14 nm research is now underway. I would not be at all surprised if “CMOS” hits the wall of fundamental physics and chemistry (on a manufacturing scale) at about 10 nm.
I am not sad by this though. On the contrary we have been doing the same thing over and over and over again for 40 years! Now we will have to get creative and invent something new! Or at least learn to write better software. That a computer with GBs (!) of RAM could feel sluggish shows how sloppy and inefficient some codes are! The “throw more hardware at it” approach will cease to work, regular programmers may once again think about resources like all embedded programers do! It is coming, the question simply is: when?